1. Field of the Invention
The present invention relates to a voltage supply circuit including a boosting circuit for boosting a power supply voltage, and a semiconductor memory.
2. Background Art
Conventionally, for example, semiconductor memories such as NAND flash memories include voltage supply circuits for supplying power supply voltages having been boosted by boosting circuits.
For example, semiconductor memories such as NAND flash memories require higher potentials than power supply voltages for writing, erasing, and reading data. Thus the voltage supply circuit of such a semiconductor memory includes a boosting circuit for boosting a power supply voltage and a voltage detecting circuit for keeping the potential at a set potential.
In the boosting circuit, MOS transistors and capacitances are connected in series and one ends of the capacitance are connected via complementary CLK and CLKB signals to boost the power supply voltage.
The voltage detecting circuit includes a voltage dividing circuit and a comparator. In the voltage detecting circuit, a boosting circuit output terminal and a ground potential are connected in series via the voltage dividing circuit, and a monitor potential outputted from the voltage dividing circuit and a reference potential are compared with each other by the comparator.
A plurality of n-type MOS transistors having sources set at a ground potential are connected from the junction of the voltage dividing resistor of the voltage dividing circuit and the gates of the transistors are each fed with a selection signal. The selection signal determines the set potential of an output from the boosting circuit. In other words, the detection level of the voltage detecting circuit can be changed.
In this case, for example, when the output from the boosting circuit is lower than the set potential, the monitor potential falls below the reference potential and the comparator switches the output to, e.g., “High”. The output activates the boosting circuits and the output from the boosting circuit is boosted in response to the CLK/CLKB signals.
Conversely, when the output from the boosting circuit is higher than the set potential, the monitor potential becomes higher than the reference potential and the comparator switches the output to, e.g., “Low”. The output deactivates the boosting circuit and interrupts the CLK/CLKB signals to stop the boosting operation of the boosting circuit.
In this way, the voltage detecting circuit activates and deactivates the boosting circuit, so that the output from the boosting circuit can be kept near the set potential.
A voltage supply circuit of the prior art includes a plurality of boosting circuits for boosting a voltage supplied from a power supply and generating an output voltage, a plurality of CP output control circuits for monitoring the output voltage and outputting signals for instructing the boosting circuits to be activated or deactivated, an oscillator fed with the outputs (voltages for performing OSC control) of the CP output control circuits, and a clock buffer circuit which is fed with the oscillation output of the oscillator and outputs signals to the boosting circuits (for example, see Japanese Patent Laid-Open No. 11-154396).
The CP output control circuits are so designed as to vary in output detecting voltage, so that a step-by-step operation is performed according to a change of the output voltage.